1. Field of the Invention
The present invention relates to a display panel driving circuit, and more specifically to a driving circuit for a display panel constituting a capacitive load, such as an AC drive type plasma display panel (abbreviated as "PDP") and an electro-luminescence (abbreviated as "EL") display.
2. Description of Related Art
Since a surface-discharge AC drive type plasma display panel has various advantages such as a thinness, a high brightness, and a high resolution, a study for enlarging the screen size is now being energetically pushed ahead as a leading display element for a wall television receiver set. In such an application to the display device, since the plasma display panel is essentially a large capacitive load, a drive circuit for the plasma display panel is designed by taking the capacitive load into consideration.
Referring to FIG. 1, there is shown a diagram illustrating a basic construction of the AC drive type plasma display panel including a conventional drive circuit. The shown plasma display panel apparatus includes a display panel 10 to be driven, a pair of data electrode drive circuits 20 for driving a number of data electrodes Xi (i=1.about.n) of the display panel 10, a scan electrode drive circuit 30 for driving a number of scan electrodes Yj (j=1.about.m) of the display panel 10, and a common electrode drive circuit 40 for driving a number of common electrodes Z of the display panel 10.
As well known to persons skilled in the art, the display panel 10 is so configured that, the data electrodes Xi are located on one surface separated from one another, and on an opposing surface which is located to face the one surface with a predetermined spacing, the scan electrodes Yj and the common electrodes Z are alternately located to extend orthogonally to the data electrodes Xi. Each of the common electrodes is located closely to but apart from a corresponding one of the scan electrode Yj, so that one common electrode and one scan electrode are paired with. All the common electrodes are connected in common at their one ends. These three kinds of electrodes Xi, Yj and Z are electrically insulated from one another, and therefore, are mutually capacitively coupled to one another.
A display cell 11, C(ij) is constituted at an intersection of one date electrode Xi and one scan electrode Yj and its associated common electrode Zj. Therefore, a number of display cells are located in the form of a matrix. A light emitting discharge is generated in a gap of the above mentioned predetermined spacing by applying an AC pulse by action of the respective drive circuits. In each application of the AC pulse, a capacitance of the electrodes associated to the display cell is charged and discharged. In certain display panels, a reactive current attributable to this charge/discharge becomes larger than a discharge current when the applied voltage exceeds a threshold voltage of the light emitting discharge.
Referring to FIG. 2, there is shown a timing chart illustrating one example of a method for driving the plasma display panel. FIG. 2 shows driving waveforms for a display period corresponding to one frame of binary image.
The display period of one frame is divided into a pre-discharge period, a data write period and a sustain discharge period. In the pre-discharge period which is a first period of each one display period, while maintaining all the data electrodes at a ground level GND, a negative erase pulse Vap is applied to all the scan electrodes, and then, a negative discharge pulse Vp is applied to all the common electrodes Z, in order to erase a display content of a preceding frame and to be ready for a wall charge for a writing of a new display data.
In the data write period which is a second period of each one display period, a line sequential writing is conducted on the basis of a new display data. For the first scan electrode Y1 of the display panel, a positive data pulse voltage Vd is applied to the data electrode Xi for a display cell to be lighted, but the data electrode Xi for a display cell not to be displayed is maintained at the ground level GND. On the other hand, a negative scan pulse voltage Vw is applied to the scan electrode Y1, so that a write discharge occurs between the scan electrode and the data electrode applied with the positive data pulse voltage Vd, with the result that the wall charge is created. Succeedingly, a similar operation is repeated for the remaining scan electrodes Y2 to Ym in the order from the second scan electrode Y2 to the final scan electrode Ym.
In the sustain discharge period following the data write period, a negative sustain pulse Vs is applied alternately and exclusively to the common electrodes Z and the scan electrodes Yj, as shown in FIG. 2, so that the discharge is sustained in cells in which the wall charge is created in the preceding writing operation. This alternate exclusive application of the sustain pulse is repeated "k" times, so that an image of one frame is display.
The following is a specific numerical example. The repetition number "k" is on the order of 200 to 500, and the sustain pulse voltage Vs is on the order of -160 V to -180 V. The scan pulse voltage Vw is on the order of -160 V to -200 V, and the erase pulse voltage Vap is on the order of -140 V to -190 V. The data pulse voltage Vd is on the order of +60 V to +80 V, and the pre-discharge pulse voltage is on the order of -300 V to -350 V.
In the driving as mentioned above of the AC drive type plasma display panel, since the applied voltage is large and the load capacitance is large, it is in some cases that the reactive power consumed in the capacitance associated with the display cells reaches 50% or more of the overall consumed electric power. In addition, a heating and a definite driving capacity of driving elements included in the drive circuits often become a problem, which will become remarkable with demands for an elevated brightness of the display and an increased amount of the display information.
In order to overcome the above mentioned problems, various proposals have been made in the prior art. For example, Japanese Patent Post-examination Publication No. JP-B-5-081912, which corresponds to U.S. Pat. No. 4,707,692, the disclosure of which is incorporated by reference in its entirety into this application, proposes a display panel driving circuit so constructed that a coil is connected to one of electrodes of a capacitive load, and an electric charge charged in display cells is recovered into a capacitance of a power supply line by use of resonance. This will be called a first prior art display panel driving circuit hereinafter.
In addition, Japanese Patent Application Pre-examination Publication No. JP-A-63-101897, which corresponds to U.S. Pat. No. 4,866,349, the disclosure of which is incorporated by reference in its entirety into this application, proposes a display panel driving circuit constructed to have a dedicated capacitor for recovering and releasing an energy by utilizing about one half of a pulse voltage. This will be called a second prior art display panel driving circuit hereinafter.
Furthermore, Japanese Patent Application Pre-examination Publication No. JP-A-5-265397, the disclosure of which is incorporated by reference in its entirety into this application, proposes a display panel driving circuit so constructed as to recover and re-use an electric power of the sustain pulse by utilizing a coil having one end connected in common to one end of diodes which have the other end connected to individual scan electrodes, respectively, so that an electric power of the sustain pulses is recovered and re-used in a time-division manner. This will be called a third prior art display panel driving circuit hereinafter.
On the other hand, the electric power consumption in the data writing period remarkably increases when the plasma display panel is used as a high quality television image display which is an estimated dominant use of the plasma display panel, because (1) the execution number of the data writing for each sub-frame as the result of the frame division for a half tone display is increased (for example, 8 data writings are required for the display for 256 gray scales), (2) the number of the data electrodes is increased for a color display (namely, becomes three times for red, green and blue), and (3) the number of required data electrodes is also increased for a wide screen display.
However, the first and second prior art display panel drive circuits becomes inevitably large in size if one coil is connected to each of independent electrodes.
Furthermore, the third prior art display panel drive circuit is so configured to cope with only the sustain discharge period which consumes a maximum electric power in the prior art plasma display panel, and therefore, can handle neither the scan pulse which is applied only one for one scan electrode in each one frame period, nor the data pulses applied to the data electrodes, which would require a high speed parallel and mixed operation of recovery and release of an electric power.
Accordingly, the disadvantage of the first to third prior art display panel drive circuits that it is not possible to recover and re-use the electric charge applied during the data write period, becomes a large problem when the plasma display panel is used as a high quality television image display,
In order to realize the electric power recovery not only in the sustain discharge period but also in the data write period, there are various problems to be solved as follows:
A first problem is to realize a number of drivers which are formed on a single integrated circuit and which can individually recover and re-use a charging and discharging electric power on each of individual electrodes and also can realize a parallel and mixed operation of the recovery and the discharge, compatibly with a high speed data.
A second problem is to realize a number of drivers and a control circuit therefor, which can realize the above mentioned operation for pulses which are different in amplitude and in potential.
A third problem is to realize a method for operating a number of drivers formed on the integrated circuit, simultaneously and in parallel.